Estimation and Synthesis for Low Power, High Performance Integrated Circuits

Estimation and Synthesis for Low Power, High Performance Integrated Circuits by Premal Buch Doctor of Philosophy in Engineering Electrical Engineering & Computer Sciences University of California, Berkeley Professor A. Richard Newton, Chair Power minimization is becoming very important for a number of reasons ranging from an increasing demand for portable computing to the problem of hot chips due to increasing clock frequencies and device counts of integrated circuits. Minimizing power dissipation of chips has an impact not only on energy savings, but also helps create more reliable chips. In this context, the advent of deep submicron technologies creates a moving target for CAD algorithms, which now need to reduce power in the existing design methodology as well as consider delay, power and area minimization from the deep submicron perspective. This thesis presents a set of algorithms for the characterization and synthesis of high performance integrated circuits with a focus on low power design. Algorithms for fast vector-dependent power simulation and vector-independent power estimation at the transistor level are presented along with a fast mixed-signal simulator used to drive the estimation. A mixed-abstraction methodology is outlined for chip-level power estimation. The logic synthesis problem is approached from two directions: optimizing a circuit for new design criteria like power dissipation in the current design methodology, and a new methodology for next generation circuit design targeting delay, power and area optimization in deep submicron technology. Statistical properties of functions and minterm probabilities in the Boolean space are analyzed and algorithms to reduce power dissipation without compromising the traditional design criteria like delay and area are presented at the technology independent and dependent level in the current static CMOS standard cell based framework. Pass transistor logic (PTL) is proposed as a promising alternative to static CMOS for deep submicron design and decomposed BDDs are proposed as a suitable logic level representation for synthesis of PTL networks. A comprehensive new synthesis flow based on decomposed BDDs is outlined for PTL design. It is shown that the proposed approach allows logic-level optimizations similar to the traditional multi-level network based synthesis flow for static CMOS, and also makes possible optimizations with a direct impact on delay, power and area of the final circuit implementation which do not have any equivalent in the traditional approach. Heuristic algorithms to synthesize PTL circuits optimized for delay, power and area in the new methodology are presented. Professor A. Richard Newton Dissertation Committee Chair